The present invention relates generally to protection of integrated circuits from electrostatic discharges and more specifically to the use of devices formed in isolated well regions for electrostatic discharge protection.
Metal oxide silicon field effect transistors (MOSFETs) are highly susceptible to damage from exposure to an electrostatic discharge (xe2x80x9cESDxe2x80x9d). The gate conductor of a MOSFET device is separated from an underlying source, drain and conductor channel semiconductor region by a very thin insulating layer. The insulating layer is typically constructed of silicon dioxide (SiO2) having a thickness of less than 100 angstroms. The break down voltage of a high quality silicon dioxide layer of such thickness may only be about 10 volts. Electrostatic voltages may range from several hundred volts to several thousand volts. Such voltages can be easily generated and discharged by a person touching the terminals of an integrated circuit, or the equipment housing the circuit. Therefore, when the gate conductor of a MOSFET device is used as an input to a packaged integrated circuit, the inadvertent application of an electrostatic voltage can destroy the input transistor.
One approach previously utilized in providing electrostatic discharge protection is to connect a two terminal silicon controlled rectifier (xe2x80x9cSCRxe2x80x9d) to the gate of the input transistor. The SCR is formed as a four layer device with alternate P-type and N-type junctions. The disadvantage with this approach is that when the SCR is fabricated in accordance with conventional integrated circuit processing steps, such SCR does not break down until the electrostatic voltage reaches forty to one hundred volts. It is apparent that with forty to one hundred volts applied to the input of a MOSFET integrated circuit, it is highly likely that the circuit will be damaged. The one hundred volt breakdown of the SCR arises from the formation of an Nwell in a P-type substrate to fabricate one junction of the four layer SCR device. This junction exhibits the largest breakdown voltage of the SCR device, which voltage must be exceeded in order to turn on the SCR.
Other attempts to provide electrostatic discharge protection include the provision of a gateless NMOS transistor connected across the input device to be protected. Under normal operating conditions, the protection device would remain in a nonconductive state, as it has no gate or conduction channel. Rather, there is formed in lieu of a conduction channel an insulating silicon dioxide which allows conduction only when a relatively high voltage is impressed between the semiconductor source and drain regions. This approach requires a substantial amount of wafer area, added input capacitance to the circuit, and is generally difficult to fabricate with a closely controlled breakdown voltage.
In addition, the MOSFETs are most effective when a plurality are arranged in parallel so that there are a plurality of paths of the ESD to ground. The drawback of this approach is that the voltage across a NMOS must first exceed the trigger voltage Vt1 for the NMOS to conduct. Once the NMOS begins conducting the voltage across the NMOS drops to a lower voltage Vsp. (This is known as the snapback effect.) The engineering problem is that not all the NMOS achieve conduction at the same instant. Therefore, the first NMOS to reach conduction will prevent the other NMOS from achieving conduction.
From the foregoing, it can be seen that a need exists for an improved method and circuit for protecting the inputs of semiconductor circuits. Particularly, a need exists for clamping electrostatic voltages to a safe level without damaging either the circuits to be protected, or the protection circuit itself.
One aspect of the present invention is an ESD protection circuit that includes a first FET and a second FET. The drain of the first FET is coupled to an ESD susceptible node and the source of the first FET is coupled to a first voltage terminal. The gate and a well of the first FET are coupled together and to the drain of the second FET. The source of the second FET is coupled to the first voltage terminal. The gate of the second FET is coupled to a second voltage terminal. The second voltage terminal is connected to a voltage source that is at the first voltage when the circuit is not powered, and at a voltage above the threshold voltage of the second FET when the circuit is powered.
The well in which the first FET is formed is electrically isolated from other wells in the substrate. The electrical isolation surrounding the well includes (1) a second-type dopant isolation regions in a first type substrate surrounding and abutting the well, (2) a substrate doped with second type doping, and (3) dielectric isolation, such as deep trench, STI, and buried oxide layer. The well may be isolated by any of these methods separately or in combination (e.g. trench isolation on sides, second-type doping on bottom).
Another aspect of the present invention is an integrated circuit chip that includes an I/O pad, a substrate, a first-type dopant well formed in the substrate, a first-type dopant contact region in the well near a surface of the substrate and resistively coupled to ground or a reference potential, and a second-type dopant contact region in the well near the surface of the substrate and coupled to the I/O pad. Shallow isolation regions separate the first-type dopant and second-type dopant contact regions on their lateral sides. A second-type dopant isolation region surrounds the well and is coupled to a voltage terminal. The first-type dopant contact region to the first-type substrate is coupled to ground.
Another aspect of the present invention is an integrated circuit chip that includes a substrate, a first-type dopant well formed in the substrate, at least one source region and at least one drain region. Each source-drain pair delimits channel regions between them in the substrate. At least one of the gates is over one of the channels regions.
The electrical isolation surrounding the well includes (1) a second-type dopant isolation regions in a first-type dopant substrate surrounding and abutting the well, (2) a substrate doped with second-type doping, and (3) dielectric isolation, such as deep trench, STI, and buried oxide layer. The well may be isolated by any of these methods separately or in combination (e.g. trench isolation on sides, second-type doping on bottom or a buried oxide layer instead of buried N layer 8 of FIG. 1.) A pad of the integrated circuit chip is connected to at least one of the drains. At least one of the gates is connected to the well, and the well is resistively coupled to ground. At least one of the source regions is coupled to ground.
Another aspect of the present invention is an integrated circuit chip that includes a substrate, a first-type dopant well formed in the substrate, at least one source region and a least one drain region. Each source-drain pair delimits the channel regions between them in the substrate. Second-type dopant isolation regions in a first type substrate surround and abut the well. Alternatively, the substrate may be of second type, in which case the substrate forms the isolation region. A pad of the integrated circuit chip is connected to at least one of the drains and the isolation region. At least one of the gates is connected to the well, and the well is resistively coupled to ground. At least one of the source regions is coupled to ground.
Another aspect of the present invention is an ESD circuit that includes a substrate, an isolated well of a first type in the substrate that is delimited by isolation regions of second type in the substrate adjacent to and beneath the isolated well. The isolated well contains a FET having a source and a drain of second type formed in the isolated well and a gate separating the source and the drain, wherein the isolated well, the source, and the gate are all coupled to a first voltage terminal, and wherein the drain is coupled to an ESD susceptible circuit node. A first-type region is contained inside the second-type isolation region, and is coupled to the ESD susceptible circuit node through a resistor. The isolation regions are coupled to a second voltage terminal.
The circuit disclosed in the preceding paragraph includes an ESD susceptible node coupled to an FET, and to a first terminal of an SCR structure through a resistor. The SCR type structure consists of alternating regions of first and second type dopants. The first region of the SCR is the first-type dopant region inside the second-type isolation region, the second region is the second-type isolation region, the third region is the first type well, and the fourth region is the second-type source region. The first terminal of the SCR consists of the first-type dopant region inside the second-type isolation region. The FET includes a well, a gate, a source, and a drain. The source forms a second terminal of the SCR structure. The second terminal of the SCR structure, the well and the gate are coupled to a second voltage terminal.